1. Field of the Invention
The present invention relates to a microcomputer configured to switch between programs in response to an occurrence of an interrupt or exception.
2. Description of Related Art
A microcomputer is designed to stop the execution of a running program and to branch to another program for executing interrupt or exception processing, in response to an occurrence of an interrupt or exception.
In this specification, “an exception” is a general term indicating exceptions in a narrow sense such as: a hardware interrupt requested by peripheral hardware incorporated in the microcomputer or in an external device connected to the microcomputer; a software interrupt caused by a system call instruction or a trap instruction written in an application program; a division by zero caused during the execution of a program; and a suspension of the processing of a running program due to an occurrence of an abnormality such as an overflow or address error.
In this specification, a term of “an exception handler” denotes a program that has an exception processing routine written therein, and be executed in the occurrence of an exception while suspending a program running before the occurrence. Moreover, a term of “an exception handler address” indicates a start address of the exception handler.
In this specification, a term of “an exception vector” denotes information indicating a location to which the processing should branch when an exception occurs. A start address (an exception handler address) of an exception handler is used as an exception vector in some cases. In other cases, a start address in a branch instruction to branch to an exception handler is used instead of a direct exception vector, and thus the exception handler itself is located at an address to which a jump is made according to the branch instruction.
In this specification, a term of “an exception handler address table” denotes a table in which exception handler addresses are arranged, or a table in which branch instructions to jump to exception handler addresses are arranged. An exception vector is used to specify each of array elements, i.e., exception handler addresses or branch instructions to jump to exception handler addresses, in the exception handler address table.
Incidentally, there are other cases where a table formed of an array of exception handler addresses is called “an exception table” or “a vector table,” and where a table formed of an array of branch instructions to jump to the respective exception handlers is called “a jump table.” In this specification, however, the two tables are collectively called “the exception handler address table.”
Furthermore, in this specification, a term of “an exception vector corresponding address” indicates the content of an exception vector. In other words, the exception vector corresponding address is an address specifying an array element in the exception handler address table.
As described above, as the exception handler address table to be referenced to at a start time of exception processing, some of conventional microcomputers use a table directly formed of an array of exception handler addresses, and other some use a table formed of an array of branch instructions to jump to the respective exception handlers.
For example, U.S. Pat. No. 6,079,015 discloses a technique of relocating memory maps between a first memory map (exception table) and a second memory map (jump table). More precisely, the first memory map directly stores exception handlers (“exception routines” in U.S. Pat. No. 6,079,015) in memory areas each predetermined corresponding to an exception cause. In contrast, the second memory map stores branch instructions to jump to the respective exception handlers (exception routines) in memory areas each predetermined corresponding to an exception cause. Here, the memory area used by the second memory map is smaller than that of the first memory map.
There is a demand for changing the size of the exception handler address table according to an operation mode of the microcomputer. This demand is particularly strong for a built-in type microcomputer for a system under severe constraints on an available memory size. For example, at a time of starting the microcomputer, a time of rewriting a flash ROM included in the microcomputer, or another time, a limitation is imposed on the available memory size while only limited kinds of exceptions (exception causes) may occur. Accordingly, when the microcomputer operates in a reduced operation mode such as an operation mode for the start-up processing or an operation mode for maintenance work like the flash ROM rewriting processing, it is desirable to reduce the exception handler address table by decreasing the number of exception vectors from that used by the microcomputer in a normal operation mode.
Japanese Patent Application Publication No. 2000-267864 discloses a technique of enhancing efficiency of memory use by reducing a memory area used as the exception handler address table (“an interrupt vector table” in JP-A No. 2000-267864) as a result of releasing a part of the memory area that is out of use as the exception handler address table. The technique disclosed in JP-A No. 2000-267864, however, is based on an idea that there is no need to prepare exception vectors (“interrupt vectors” in JP-A No. 2000-267864) corresponding to out-of-use exception causes (“interrupt factors” in JP-A No. 2000-267864), that is, an idea that there is no need to hold exception handler addresses (“interrupt program start address” in JP-A No. 2000-267864) corresponding to out-of-use exception causes. Based on this idea, the exception handler address table is reduced in size without holding the exception handler addresses corresponding to the out-of-use exception causes. In other words, the technique disclosed in JP-A No. 2000-267864 allows the size of the exception handler address table to be reduced, but does not make a change in correspondences between exception causes and exception vector on a one-to-one basis.
Even though possible exception causes are limited in the foregoing example such as a case of starting the microcomputer, or rewriting the flash ROM, the microcomputer needs to deal with an unanticipated contingency that an instruction to request unexpected exception processing is inputted. To this end, the microcomputer in the reduced operation mode must be ready to provide at least some of exception handlers corresponding to exception causes generally considered to occur only in the normal operation mode. Thus, the technique disclosed in JP-A No. 2000-267864 has a limitation on the number of reducible exception vectors. That is to say, the conventional microcomputer lacks the flexibility in changing correspondences between exception causes and exception vectors, and thereby is incapable of reducing the exception handler address table sufficiently when such reduction is required.